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<section-title-en>2.12 Interrupts</section-title-en>
<section-title-ch>2.12 中断</section-title-ch>
<p-en>
	Peripherals use interrupts to signal the occurrence of an event that must be handled by system software. For example, a keyboard triggers interrupts when a key is pressed or depressed. System software also relies on interrupts to implement preemptive multi-threading.
</p-en>
<p-ch>
	外围设备使用中断来提示必须由系统软件处理的事件的发生。例如，键盘在按下或压下某个键时，就会触发中断。系统软件也依靠中断来实现先发制人的多线程。
</p-ch>
<p-en>
	Interrupts are a kind of hardware exception (§2.8.2). Receiving an interrupt causes an execution core to perform a privilege level switch and to start executing the system software's interrupt handling code. Therefore, the security concerns in §2.8.2 also apply to interrupts, with the added twist that interrupts occur independently of the instructions executed by the interrupted code, whereas most faults are triggered by the actions of the application software that incurs them.
</p-en>
<p-ch>
	中断是一种硬件异常（§2.8.2）。接收到一个中断会导致执行核进行权限级别的切换，并开始执行系统软件的中断处理代码。因此，§2.8.2中的安全问题也适用于中断，但有一个额外的变化，即中断的发生与被中断代码执行的指令无关，而大多数故障是由引起中断的应用软件的行为所触发的。
</p-ch>
<p-en>
	Given the importance of interrupts when assessing a system's security, this section outlines the interrupt triggering and handling processes described in the SDM.
</p-en>
<p-ch>
	鉴于中断在评估系统安全性时的重要性，本节概述了SDM中描述的中断触发和处理过程。
</p-ch>
<p-en>
	Peripherals use bus-specific protocols to signal interrupts. For example, PCIe relies on Message Signaled Interrupts (MSI), which are memory writes issued to specially designed memory addresses. The bus-specific interrupt signals are received by the I/O Advanced Programmable Interrupt Controller (IOAPIC) in the PCH, shown in Figure 20.
</p-en>
<p-ch>
	外围设备使用总线专用协议来发出中断信号。例如，PCIe依靠消息信号中断(MSI)，它是向特殊设计的内存地址发出的内存写入。总线特定的中断信号由PCH中的I/O高级可编程中断控制器（IOAPIC）接收，如图20所示。
</p-ch>
<p-en>
	The IOAPIC routes interrupt signals to one or more Local Advanced Programmable Interrupt Controllers (LAPICs). As shown in Figure 22, each logical CPU has a LAPIC that can receive interrupt signals from the IOAPIC. The IOAPIC routing process assigns each interrupt to an 8-bit interrupt vector that is used to identify the interrupt sources, and to a 32-bit APIC ID that is used to identify the LAPIC that receives the interrupt.
</p-en>
<p-ch>
	IOAPIC将中断信号路由到一个或多个本地高级可编程中断控制器（LAPIC）。如图22所示，每个逻辑CPU都有一个LAPIC，可以从IOAPIC接收中断信号。IOAPIC路由过程将每个中断分配给一个8位的中断向量，用于识别中断源，并分配给一个32位的APIC ID，用于识别接收中断的LAPIC。
</p-ch>
<p-en>
	Each LAPIC uses a 256-bit Interrupt Request Register (IRR) to track the unserviced interrupts that it has received, based on the interrupt vector number. When the corresponding logical processor is available, the LAPIC copies the highest-priority unserviced interrupt vector to the In-Service Register (ISR), and invokes the logical processor's interrupt handling process.
</p-en>
<p-ch>
	每个LAPIC使用256位的中断请求寄存器(IRR)，根据中断向量号跟踪它所接收到的未服务中断。当相应的逻辑处理器可用时，LAPIC将最高优先级的无服务中断向量复制到在用寄存器（ISR），并调用逻辑处理器的中断处理过程。
</p-ch>
<p-en>
	At the execution core level, interrupt handling reuses many of the mechanisms of fault handling (§2.8.2). The interrupt vector number in the LAPIC's ISR is used to locate an interrupt handler in the IDT, and the handler is invoked, possibly after a privilege switch is performed. The interrupt handler does the processing that the device requires, and then writes the LAPIC's End Of Interrupt (EOI) register to signal the fact that it has completed handling the interrupt.
</p-en>
<p-ch>
	在执行核心层，中断处理重用了许多故障处理的机制（§2.8.2）。LAPIC的ISR中的中断向量号被用来定位IDT中的中断处理程序，处理程序被调用，可能是在执行权限切换之后。中断处理程序进行设备所需的处理，然后写入LAPIC的End Of Interrupt（EOI）寄存器，发出信号，表明它已经完成了对中断的处理。
</p-ch>
<p-en>
	Interrupts are treated like faults, so interrupt handlers have full control over the execution environment of the application being interrupted. This is used to implement pre-emptive multi-threading, which relies on a clock device that generates interrupts periodically, and on an interrupt handler that performs context switches.
</p-en>
<p-ch>
	中断被当作故障处理，所以中断处理程序可以完全控制被中断的应用程序的执行环境。这是用来实现先发制人的多线程的，它依赖于一个周期性产生中断的时钟设备和一个执行上下文切换的中断处理程序。
</p-ch>
<p-en>
	System software can cause an interrupt on any logical processor by writing the target processor's APIC ID into the Interrupt Command Register (ICR) of the LAPIC associated with the logical processor that the software is running on. These interrupts, called Inter-Processor Interrupts (IPI), are needed to implement TLB shootdowns (§2.11.5).
</p-en>
<p-ch>
	系统软件可以通过将目标处理器的 APIC ID 写入与软件运行的逻辑处理器相关联的 LAPIC 的中断命令寄存器 (ICR) 中，在任何逻辑处理器上引起中断。这些中断称为处理器间中断（IPI），是实现TLB击落所需要的（§2.11.5）。
</p-ch>

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